双栅肖特基源漏MOSFET的阈值电压模型

通过求解泊松方程得到了双栅肖特基势垒MOSFET的解析模型. 这个解析模型包括整个沟道的准二维电势分布和适用于短沟双栅肖特基势垒MOSFET的阈值电压模型.数值模拟器ISE DESSIS验证了模型结果.     

Influence of Ballistic Effects in Ultra-Small MOSFETs

Single Gate (SG) and Double Gate (DG) MOSFETs with strained and unstrained Si channel are studied using semi-classical Monte Carlo simulation to investigate the influence of ballistic electrons. We analyze how the intrinsic ballisticity B_int, directly deduced from accurate counting of scattering events undergone by carriers in the channel, depends on channel length, channel doping, strain, MOS architectures and bias. Besides, we show that the intrinsic ballisticity B_int seems to be a relevant parameter to explain the performance of small devices. It is highlighted that in undoped channels shorter than 50 nm, quasi-ballistic effects are responsible for a significant improvement in the on-current. However, for channel length smaller than about 30 nm (B_int > 20%) the current tends to the ballistic limit and the increase in intrinsic ballisticity has a decreasing impact on the current.     

一种基于载流子的双栅MOSFET解析模型

提出一种全新的基于载流子求解的双栅MOSFET解析模型. 针对无掺杂对称双栅MOSFET结构，该模型由求解泊松方程的载流子分布和Pao-Sah电流形式直接发展而来. 发展的解析模型完全基于MOSFET的基本器件物理进行直接推导,结果覆盖了双栅 MOSFET所有的工作区:从亚阈到强反型和从线性到饱和区,不需要任何额外假设和拟合参数. 模型的预言结果被2D数值模拟很好地验证，表明该解析模型是一个理想的双栅MOSFET建模架构.     

Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nm and the 20 nm n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher Ion/Ioff ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs.     

Static and low-frequency noise characterization in submicron MOSFETs for memories cells applications

In this paper, we present the extraction of oxide traps properties of n-metal-oxide-semiconductor (N-MOS) field effect transistors with W×L=0.5×0.1 μm² using low-frequency (LF and random telegraph signal) noise and static I(V) characterizations. The impact of oxide thickness, on static and noise parameters is analyzed. Static measurements on N-MOS devices with different tunnel oxide thickness show anomalies (a significant increase in V_t values for low temperature and kink effect) attributed to traps located in the oxide. From LF noise analysis we find that 1/f noise stems from carrier number fluctuations. The slow oxide trap concentration deduced from the noise data is about 10¹⁵ eV/cm³ in agreement with the state-of-the-art gate oxides. Finally, drain current RTS amplitude as large as 10% have been observed.     

A field-effect electron mobility model for SiC MOSFETs including high density of traps at the interface

Besides its favorable physical properties, high performant MOSFETs (metal-oxide-semiconductor field-effect transistors) fabrication in silicon carbide (SiC) remains an open issue due to their low channel mobility values. The effect of charge trapping and the scattering at interface states have been invoked as the main reasons for mobility reduction in SiC thermal oxidized MOS gated devices. In this paper, we propose a compact electron mobility model based on the well-established Lombardi mobility model to reproduce the mobility degradation commonly observed in these SiC devices. Using 2D electrical simulations along with the proposed model and taking into account interface traps Coulomb scattering, the experimental field-effect mobility of 4H-SiC MOSFET devices has been fitted with a good agreement.     

High frequency performance of nano-scale ultra-thin-body Schottky-barrier n-MOSFETs

The high frequency performances of nano-scale ultra-thin-body (UTB) Schottky-barrier n-MOSFETs (SB-nMOSFETs) are investigated using 2D full-band self-consistent ensemble Monte Carlo method. The UTB SB-nMOSFET devices offer excellent RF performance with high values of f T and f max.The significant dependence of f T and f max on gate voltage and weak dependence on barrier height are demonstrated.Meanwhile,the significant dependence of g m and g ds on both gate voltage and SB height are shown. Moreover,the sca...     

Threshold voltage modeling for dual‐metal quadruple‐gate (DMQG) MOSFETs

In this paper, a three‐dimensional (3D) model of threshold voltage is presented for dual‐metal quadruple‐gate metal‐oxide‐semiconductor field effect transistors. The 3D channel potential is obtained by solving 3D Laplace's equation using an isomorphic polynomial function. Threshold voltage is defined as the gate voltage, at which the integrated charge (Q_inv) at the ‘virtual‐cathode’ reaches to a critical charge Q_th. The potential distribution and the threshold voltage are studied with varying the device parameters like gate metal work functions, channel cross‐section, oxide thickness, and gate length ratio. Further, the drain‐induced barrier lowering has also been analyzed for different gate length ratios. The model results are compared with the numerical simulation results obtained from 3D ATLAS device simulation results. Copyright © 2015 John Wiley & Sons, Ltd.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

A 2-D Semi-Analytical Model of Double-Gate Tunnel Field-Effect Transistor Xu Huifang (许会芳), Dai Yuehua*(代月花), Li Ning(李宁), Xu JianBin(徐建斌)

文中提出了一种双栅隧穿场效应晶体管(DG TFET)的二维半解析模型。通过在栅绝缘层和沟道区引入两个矩形源,运用半解析法和特征函数展开法求解二维泊松方程,得到电势的二维半解析解。解的结果是一个特殊函数,为无穷级数表达式。基于电势模型,求出最短隧穿长度( )和平均电场( ),运用Kane模型得到漏极电流。新模型考虑了移动电荷对电势的影响以及漏源电压对隧穿参数 和 的影响。文中计算了不同漏源电压,不同硅膜厚度,栅介质层厚度和栅介质层常数下的表面势和漏极电流。结果表明,新模型与仿真结果吻合。这将有助于DG TFET的优化设计,同时,也加深了DG TFET器件对电路结构设计的规划。